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PeopleAlberto Bonanno
Alberto Bonanno's foto

Alberto Bonanno

PhD Student

IIT@POLITO


City Torino
Phone 0110903431

Bio

Alberto Bonanno graduated in Electronic Engineering at Politecnico di Torino in 2005.
He also holds Dr.Eng. degree in Electrical Engineering from Ecole Polytechnique Federale de Lausanne during a double degree project.
From 2005 to 2008 he worked in a private company on the development of EDA tools for low-power IC design.
He joined Politecnico di Torino in November 2008 for working on the design of Pirelli's smart sensor system.
His research was focused on low-power digital IC design until he joined the Italian Institute of Technology in 2011 as PhD student.
Now, his research interests include several aspects of mixed-signal IC design for developing new generation of read-out chips conceived for nanomaterial sensing

Projects

Micro4Nano (M4N)

Space human robotics requirements are playing the role of sophisticated technology driver for next generation MEMS and NEMS. The development of space certified micro and nano technologies allows design of space application specific micro and nano sensors and actuators, moreover it permits basic investigations on processes and integration technologies that have to be certified or even implemented in space conditions, (i.e. to take benefit of space environmental conditions for fabrication and “in-situ” preparation and conditioning).

The specific application requirements demand other relevant investigation field regarding how to implement not “single point” MEMS or NEMS, but linear, surface and volume distributed array of micro and nano sensors (and actuators). This requirement becomes of extreme relevance for practical application and implies a system level approach and architecture selection alongside the development of new and dedicated devices.

The contribution is basically addressed to the above objectives, however the activities are not limited to space human robotics tasks, but will produce results useful to everyday applications and in general to the evolution of MEMS/NEMS devices, both in terms of functionalities (by embedding nano- and bio- results), than in terms of MEMS architecture. Such evolution scheme will open to new applications, systems miniaturization and human-machine interfaces.

The main focus in this first phase of the research activities is bridging nanotech results to the space application in a faster way, filling the gap existing between technological discoveries and their exploitation.

Present MEMS sensors are based on one silicon chip integrating microelectronic circuitry with one or few microelectromechanical parts, used as active elements often operating in closed control loop. The demand of distributed array of microsensors is recently emerging and representing one of the most relevant research topics in the field. Many efforts finding solutions to distributed sensing are considering the so called “no Moore” electronic devices, based on semiconducting polymer devices and circuits. We believe that most of practical achievements in a mid- and short-term can be accomplished by designing dedicated silicon based ICs to be distributed in the media, by minimizing size, cost of the silicon portions. The media can be as simple as a flexible substrate, where nano-materials will supply peculiar properties, i.e. sensing, actuation, energy and communication accordingly.

Besides achieving functionalities similar to single chip MEMS, the approach will improve the management of nano-material properties according to external controls and environment, such as space conditions.

Other Publications

BONANNO A, BOCCA A, SABATINI M (2011). "Energy analysis methods and tools for modelling and Optimizing monitoring tyre systems." - Design, Automation & Test in Europe Conference & Exhibition (DATE), 14-18 Marzo 2011,

Bonanno A., Bocca A., Macii A., Macii E., Poncino M. (2010) "Data-Driven Clock Gating for Digital Filters". - LECTURE NOTES IN COMPUTER SCIENCE, vol. 5953/2010, pp. 96-105.

 

Bonanno A., Bocca A., Macii A., Macii E. (2010) "Power-Aware Partitioning of Data Converters". - 18th IEEE/IFIP International Conference on VLSI and System On Chip (VLSI-SOC), Madrid (ES)

Benini L., Bonanno A., Bocca A., Macii A., Macii E., Nagel J.L., Piguet C., Poncino M. (2010)  "A refinement methodology for clock gating optimization at layout level in digital circuits." - JOURNAL OF LOW POWER ELECTRONICS, vol. 6 n. 1, pp. 44-55.

 

 

 

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